Design Challenges in Subthreshold Interconnect Circuits

As technology advances to giga-scale integration level, global interconnect resource becomes increasingly valuable in a VLSI chip. This is due to the exponential growth of the total number of interconnects/wires as the feature size of MOS transistors decreases in scaled deep submicron CMOS technologies. Interconnect length, however, has not scaled down with feature size and remains long relative to other on-chip geometries. Interconnects are metal or polysilicon wires which connect billions of active devices to carry signals within a VLSI chip. There are a number of such wires in the whole chip. Of these, the length of long interconnects in large chips is of the order of 10 mm. Interconnect and device performance in VLSI circuits depends on materials, geometry, and technology. With the dimensional scaling of technology, technological device and interconnect challenges have been closely examined by different researchers [28–33]. The delay in VLSI chips is due to active devices and interconnects. To avoid prohibitively larger delays, designers scale down global interconnect dimensions more slowly than the transistor dimensions [34]. Rather, reverse scaling is preferred for the global interconnects. Interconnects also cause excessive power to be dissipated. In recent years, there has been a compelling demand for ultra-low-power devices to ensure longer battery lifetimes. Subthreshold circuits are ideally suited for applications where minimizing energy per operation is of prime importance [35–36]. Subsequently, the benefits from ultra-low energy operation have carved out a significant niche for subthreshold circuits. Furthermore, subthreshold circuits show exponential susceptibility to the process and temperature variations. Therefore, subthreshold operating region has made the design of energy-constrained robust ultra-low-power systems a very challenging design task. The present chapter reviews in detail the various aspects of buffer-driven long interconnect under subthreshold for ultra-low-power logic and the other associated problems. These are presented in the subsequent sections.